The present disclosure generally relates to using test patterns to verify and validate a processor, and more specifically, to techniques for reducing the testing time associated with executing a test pattern on a processor for verification and validation.
The shippable product quality level (SPQL) (also referred to as shipped product quality loss) associated with a given shipment of manufactured chips to a customer plays an important role in high volume chip production. The SPQL for a shipment of manufactured chips, in general, refers to the ratio of failing (or deficient) chips to all chips shipped to a customer. For example, a one percent SPQL generally means that for every one hundred chips that are shipped to a customer, only one of the chips is deficient (or doesn't meet the customer's performance requirements). Having a high SPQL for a shipment of chips is generally undesirable. Further, failing to meet a targeted SPQL for a shipment of chips can lead to financial loss for the chip manufacturer. As such, chip manufacturers are increasingly concerned with reducing the SPQL and/or accurately determining the SPQL for manufactured chips before they are shipped to a customer.
To reduce and/or determine the SPQL, chip manufacturers typically employ processor testing tools to screen for defective chips that are produced from the manufacturing process. These testing tools typically use a wide variety of test patterns to verify and validate a system design for a processor. The goal of such tools is typically to generate the most stressful test pattern for a processor to ensure that the processor will meet the customer's performance requirements. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. As such, typically a large amount of test cases are usually generated in order to sufficiently test a processor.
Verifying and validating a processor using test pattern(s) generally includes three stages: (1) a test pattern generation stage; (2) a test pattern loading stage; and (3) a test pattern execution stage. During the execution stage, the processor typically processes the instructions (in a test case) in stages (often referred to as the processor pipeline). For example, the processor typically has to undergo a fetch stage, decode stage, and a dispatch stage before the instruction is executed. Going through all of these stages, however, generally increases the amount of time associated with testing a large number of test cases for a processor. Thus, it may be desirable to reduce the time associated with executing test cases for verifying and validating a processor.